RetroHub AI ships software today (the Studio arm). biFROST is the hardware arm — an R&D program to move data as light between standard silicon, and the staged plan to build it.

At 112–224 Gbps per lane, copper between chips hits a physics ceiling: skin-effect loss, resistive heat, sub-meter reach, rigid topology. biFROST moves the long-reach, high-speed links to light — picks and shovels for AI's scale-out.
Every dB lost in copper becomes heat a facility must remove, and usable trace length collapses at 112+ Gbps. The interactive copper-vs-optical model lives on the program page.
The honest link-by-link map. Optics takes the long-reach, high-speed SerDes; the bridge port is real custom silicon (a retimer + optical front end); the value is reach, bandwidth density, and energy-per-bit — never latency.

Desktop tooling is our prototype breadboard — not our production line. The industrial step moves the fabric to a photonics foundry and the bridge to merchant silicon.
Desktop direct-ink-write (Voltera-class) tooling to prove coupling, materials, and bridge logic at low speed — cheap, non-cleanroom, fast. Our breadboard, not our factory.
Optical fabric on a foundry SiN / laser-direct-write process; merchant retimer + VCSEL-driver/TIA silicon for the bridge; 112G characterization via shared Canadian facilities (CMC Microsystems, NRC CPFC, university labs).
Every hardware program crosses these milestones. Here are ours — the challenge, and our approach. Every milestone reflects a rigorous internal technical review.
Challenge — Get low-loss light through a manufacturable waveguide.
Our approach — Prototype on desktop tooling, then industrialize on a foundry SiN / laser-direct-write process via Canadian fab access.
Challenge — Couple light in and out cheaply and reliably at scale — the real cost driver.
Our approach — A per-port coupling budget and assembly-yield model; passive-alignment and array approaches (including microLED arrays under evaluation).
Challenge — The port must speak PCIe/CXL and drive light at 112G and beyond.
Our approach — Integrate merchant retimer + VCSEL-driver/TIA silicon now, with a path to our own bridge ASIC.
Challenge — Multiply bandwidth without fragile wavelength tricks.
Our approach — Spatial parallelism — many multimode cores — rather than wavelength-division in polymer.
Challenge — Stand apart from well-funded incumbents.
Our approach — An AMD-compatible demo leading to partnership, standards engagement (CXL / UCIe / UALink / OIF), and sovereign Canadian manufacturing.
Challenge — Make today's fabric carry tomorrow's optical compute.
Our approach — Architect the interconnect fabric to host compute-in-light components as they mature — the frontier North Star.
biFROST turns a research leader into a hardware producer — retained IP, skilled jobs, export revenue — built on real Canadian photonics heritage (Ottawa's cluster, NRC CPFC, CMC Microsystems) and its shared fabrication infrastructure.

Winning optical-interconnect companies are billion-dollar outcomes — and one just exited.
Peers build optics inside their own packages for their own silicon (Ayar, Lightmatter, Celestial, POET, Avicena). biFROST moves data as light and retrofits anyone's standard silicon. Photonic-compute players like Q.ANT are complements our fabric can host — not competitors.
A lean Phase-1 wedge, with the larger raises staged after a bench demo de-risks the tech. Canadian shared photonics infrastructure keeps capex low and is itself the sovereignty story. biFROST is grant-aligned across:
Program eligibility and structure vary and are pursued on their own timelines; nothing here represents an awarded grant.
Solve today's copper interconnect ceiling — move data as light between standard silicon. The fundable, defensible wedge.
The North Star: compute in light. The fabric we build for Track A is deliberately architected to host optical-compute components — a sovereign optical-compute platform. A long-horizon frontier, not a near-term claim.
biFROST is early-stage experimental development. If you work in photonics, additive manufacturing, HPC infrastructure, or Canadian innovation funding, we'd like to talk.